1. Field of the Invention
The present invention relates to an integrated semiconductor circuit device, more particularly, it relates to an integrated semiconductor device for generating a switching control signal. The device, according to the present invention, can be used for a semiconductor memory device with a redundant circuit, such as, for example, an erasable programmable read only memory (EPROM).
2. Description of the Prior Art
In order to enhance the yield of semiconductor memory chips with a large memory capacity, these chips are produced with a structure having a redundant circuit.
For example, in a read only memory having eight parallel outputs, memory cell arrays for nine bits including one redundant memory cell array are provided. The first through the eighth memory cell arrays are the regular memory cell arrays, while the ninth memory cell array is the redundant memory cell array.
When a failure occurs in any of the regular memory cell arrays, the ninth memory cell array is connected in place of the failed regular memory cell array, so that the normal operation of the device is maintained. This switching of the connection from the regular memory cell array to the redundant memory cell array is carried out by a switching control signal generation circuit. The function of this circuit is to decide whether a fuse should be in a conductive or nonconductive state.
The output of such a prior art switching control signal generation circuit is sent to a switching circuit, and the switching from a failed memory cell array to the redundant memory cell array is made by blowing the fuse.
However, in this prior art circuit the current flows through a pull-down resistor when the fuse is not blown, and the power consumption due to this current in the pull-down resistor is wasteful and causes other problems.
That is, the peripheral circuits formed by complementary MOS field effect transistors around a semiconductor memory device have the advantage of a lower power consumption. For example, the current in the peripheral circuits can be reduced to the order of 10.sup.-9 A. However, in this prior art circuit, the current flowing through the pull-down resistor tends to be increased to the order of 10.sup.-6 A, and may reach up to 50.times.10.sup.-6 A. If such a current flows in the circuit, the advantage of using complementary MOS field effect transistors will be lost, and the advantage of using a redundant circuit cannot be fully appreciated.